Both in the context of fabrication and in the context of handling, these thinned semiconductor wafers or thinned semiconductor chips have considerable disadvantages since they are mechanically jeopardized and nevertheless have to be provided with wiring structures on their top sides and contact layers on their rear sides. As described in the patent application DE 10 2004 054 147, for fabrication and handling the semiconductor wafers or semiconductor chips are fixed onto intermediate carriers in order to absorb the loadings that occur during handling and fabrication.
One disadvantage of fixing on an intermediate carrier is the additional fabrication outlay in fitting and removing the intermediate carrier, which not only may be associated with the contamination of the high-purity semiconductor material with contaminants by the material of the intermediate carrier, but also is associated with an increased risk of breaking for the thinned semiconductor wafer or the thinned semiconductor chip.
In order to combat this risk of breaking, it is necessary even for thinned semiconductor wafers to have a minimum thickness in order to be able to produce self-supporting semiconductor chips therefrom and process them further, even though the active region in many cases makes up only a fraction of the semiconductor chip thickness. The requirement in the case of power semiconductor wafers for depositing suitable monocrystalline silicon epitaxial layers on a self-supporting monocrystalline silicon substrate also requires a minimum thickness of the silicon substrate. This is associated with the additional disadvantage that an increased minimum source resistance has to be accepted in the case of power semiconductor components and hitherto has not been able to be reduced any further.
In this respect, FIG. 9 shows a schematic cross section through a power semiconductor chip 11 of a conventional power semiconductor component 2. A power semiconductor component of this type is constructed on a highly conductive monocrystalline silicon substrate 6 and has, on the top side 19 of the monocrystalline silicon substrate, a silicon layer 12 adapted to the requirements of the power semiconductor device for a corresponding drift path. A gate-source structure 13 is introduced in the upper region of the epitaxial layer 12, which structure, for its part, influences the total on-state resistance of a power semiconductor device of this type through the series connection of the resistances RM as metal resistance of the source metallization, RS as source resistance, RC as channel resistance in a body zone 23 and also RJ as pn junction resistance.
A not insignificant portion of the total on-state resistance is contributed by the resistance Re of the pure epitaxial material of the drift path. A considerable proportion is added to this by the series connection of the source resistance RS, which, in accordance with the explanations above, is unavoidable even in the case of thinned self-supporting monocrystalline semiconductor wafers. By contrast, the contribution of the rear side electrode 3 on the rear side of the monocrystalline silicon substrate 6 is negligibly small in comparison with the abovementioned series resistances that determine the on-state resistance of the power semiconductor component 2.
However, such rear side metallizations restrict the thermal application range of the power semiconductor elements since they tend toward migration and toward reaction with the semiconductor material with the formation of spikes, so that the theoretical limit of the thermal loadability of a semiconductor material, such as silicon, may in part not be fully exhausted. Moreover, thermal process steps after a metallization are restricted to low temperatures by the metal materials, which is associated with the disadvantage that hitherto metallization processes in semiconductor technology have, in principle, been permitted to be used only in the final phase of component production. The tendency of metals to occupy low impurity levels in the band gap range in the case of undesired indiffusion into the semiconductor wafers can also distort the properties of the semiconductor structures.